The present invention relates to a flip chip packaging structure and a related packaging method.
As shown in FIG. 19, a flip chip packaging technique is applicable to a bonding structure between a semiconductor chip 110 and a substrate 100. According to the structure shown in FIG. 19, a pad 111 is formed on an active face of the semiconductor chip 110. A bump 112, formed on the pad 111, serves as a bonding member for connecting the pad 111 to the substrate 100. Furthermore, a pad 101, provided on the substrate 100, serves as a bonding member for connecting the substrate 100 to the semiconductor chip 110. The bump 112 provided on the chip is connected to the pad 101 provided on the substrate by thermocompression bonding or ultrasonic welding.
It is a recent trend that the semiconductor chip 110 is highly integrated and accordingly the size W1 of the pad 111 provided on the semiconductor chip 110 and a pitch P1 between two neighboring pads 111 are very small. The size of the bump 112 formed on the pad 111 is small, correspondingly. When the semiconductor chip 110 is flip chip bonded to the substrate 100 via the bump 112, it is necessary to adjust the size of the pad 101 formed on the substrate 100 so as to fit to the pitch P1 of the pad 111 provided on the semiconductor chip 110. Accordingly, the size of the pad 101 formed on the substrate 100 is small when the pitch between neighboring pads 111 provided on the semiconductor chip 110 is narrow.
The semiconductor chip 110 and the substrate 100 are bonded in the following manner.
First, by plating or with discharge, a ball is formed on the pad 111 provided on an active face of the semiconductor chip 110. Then, the ball is press welded to the pad 111 under given heat or ultrasonic wave so as to form the bump (i.e. projected electrode) 112 on the pad 111.
Then, the semiconductor chip 110 is mounted on the substrate 100 under a condition that semiconductor chip 110 is faced down. The bump 112 is mechanically and electrically bonded to the pad 101 provided on the substrate 100 under applied heat and pressure. Furthermore, for the purpose of enhancing the bonding reliability, a clearance between the semiconductor chip 110 and the substrate 100 is filled with an underfill member (e.g. a thermosetting epoxy resin) 120.
When the size Φ20 of the bump 112 is small, a gap G to be formed after accomplishing the bonding operation between the semiconductor chip 110 and the substrate 100 is small correspondingly. This results in reduction in a stress relaxing capability of the underfill member 120 which can relax a thermal stress if caused due to a thermal expansion coefficient difference between the substrate 100 and the semiconductor chip 100. Furthermore, a bonding area between the bump 112 and the pad 101 provided on the substrate is small, which results in deterioration in the bonding reliability against the above-described thermal stress.
From the foregoing reasons, this conventional bonding technique cannot be preferably applied to electronic control apparatuses installed in engine rooms or any other devices which are subjected to severe temperature environments.